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MIDTERM PROJECT EE 380 CONTROL ENGINEERING I For the closed-loop control system shown in Figure 1 the design specifications are: DS1. Zero steady-state error to a step input DS2. Steady-state error due to a ramp input of less than 0.25. DS3. Percent overshoot less than 5% to a step input DS4. Settling time less than 2 seconds to a step input process R(s) Y(s) controller 1 (s+2)(s+8) Gc(s) Figure 1 1. Sketch the admissible region of the s-plane for the closed-loop poles such that DS3 and DS4 are satisfied. 2. Consider first a proportional (P) controller: Gc(s) = K.

MIDTERM PROJECT EE 380 CONTROL ENGINEERING I For the closed-loop control system shown in Figure 1 the design specifications are: DS1. Zero steady-state error to a step input DS2. Steady-state error due to a ramp input of less than 0.25. DS3. Percent overshoot less than 5% to a step input DS4. Settling time less than 2 seconds to a step input process R(s) Y(s) controller 1 (s+2)(s+8) Gc(s) Figure 1 1. Sketch the admissible region of the s-plane for the closed-loop poles such that DS3 and DS4 are satisfied. 2. Consider first a proportional (P) controller: Gc(s) = K. Check if DS1 and DS2 are satisfied. 3. Consider a proportional-integral (PI) controller: Gc(s) = KP +KI /s. Determine the range of values for KP and KI for which the closed-loop system is stable. 4. Determine an admissible range of values for KI such that DS2 is satisfied. 5. Use rltool to determine a set of admissible controller parameters: a. Place the pole of the controller and vary the zero such that the system closedloop poles are placed in the admissible region determined at 1. b. Determine the controller parameters. 6. Plot the system step response and analyze DS1 DS3 and DS4. 7. Plot the system ramp response and analyze DS2.

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